Method and integrated circuit for bit line soft programming (BLISP)

ABSTRACT

A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

BACKGROUND OF THE INVENTION.

1. Field of Invention

This invention relates to floating gate memory devices, such as flashmemory, and in particular to methods and circuits for repairingover-erased floating gate memory cells.

2. Description of Related Art

Non-volatile memory design based on integrated circuit technologyrepresents an expanding field. Several popular classes of non-volatilememory are based on arrays of floating gate memory transistors that areelectrically erasable and programmable.

The act of programming a memory array of floating gate memorytransistors in one popular approach involves injecting the floating gateof addressed cells with electrons which causes a negative charge toaccumulate in the floating gate and the turn-on threshold of the memorycell to increase. Thus, when programmed, the cells will not turn on,that is, they will remain non-conductive when addressed with readpotentials applied to the control gates. The act of erasing a cellhaving a negatively charged floating gate involves removing electronsfrom the floating gate to lower the threshold. With the lower threshold,the cell will turn on to a conductive state when addressed with a readpotential to the control gate. For an opposite polarity array,programming involves selectively removing electrons from the addressedcells' floating gates.

Floating gate memory cells suffer the problem of over-erasure,particularly when erasing involves lowering the threshold by removingelectrons from the floating gate. During the erase step, over-erasureoccurs if too many electrons are removed from the floating gate leavinga slight positive charge. The positive charge biases the memory cellslightly on, so that a small current may leak through the memory evenwhen it is not addressed. A number of over-erased cells along a givendata line can cause an accumulation of leakage current sufficient tocause a false reading.

In addition to causing false readings, when floating gate cells areover-erased, it makes it difficult to successfully reprogram the cellsusing hot electron programming, particularly with embedded algorithms inthe integrated circuits. This difficulty arises because the programcurrent will be large and, due to series resistance, the effectiveV_(DS) across cell will drop so that the electron injection efficiencywill decrease.

Further, because the erase and program operations can affect differentcells in a single array differently, floating gate memory designs ofteninclude circuitry for verifying the success of the erasing andprogramming steps. See, for instance, U.S. Pat. No. 4,875,118, entitledVOLTAGE MARGINING CIRCUIT FOR FLASH MEMORY, invented by Jungroth. If thearray does not pass erase verify, the entire array is usually re-erased.The re-erase process can aggravate over-erased cells in the array.

One solution to the over-erase problem associated with the eraseverification process is disclosed in U.S. Pat. No. 5,414,664, FLASHMEMORY WITH BLOCK ERASE FLAGS FOR OVER-ERASURE PROTECTION, issued to Linet al. on May 9, 1995, which shows a method and a device where onlythose blocks which fail the erase verify operation are re-erased.Accordingly, a re-erase of the entire array after each verify operationis not required. This mitigates the over-erase phenomenon, but does notsolve it entirely.

Thus, a repair process has been developed to correct over-erased cells.U.S. Pat. No. 5,233,562, entitled METHODS OF REPAIRING FIELD-EFFECTCELLS IN AN ELECTRICALLY ERASABLE AND ELECTRICALLY PROGRAMMABLE MEMORYDEVICE, issued to Ong, et al., describes processes for such repair usingso-called drain disturb, source disturb or gate disturb techniques.After each repair in the Ong patent, a time-consuming repairverification operation of the entire array is provided. See, also, U.S.Pat. No. 5,416,738 to Shrivastava for further background information.

Another attempt to solve the over-erase problem is described in U.S.Pat. No. 5,546,340, entitled NON-VOLATILE MEMORY ARRAY WITH OVER-ERASECORRECTION, issued to Hu et. al. Hu describes a negatively biasedsubstrate. Hu describes bulk correction of over-erased devices within anarray. Hu describes bulk correction of an array of over-erased devicesas carried forth in a convergence technique which utilizes higherfloating gate injection currents.

A low current method of programming flash EEPROMS is described in U.S.Pat. No. 5,487,033, entitled STRUCTURE AND METHOD FOR LOW CURRENTPROGRAMMING OF FLASH EEPROMS, issued to Keeney et. al. Keeney indicatesthat a control gate voltage may be stepped or ramped from a minimumvalue to a maximum value to further reduce the peak channel current andto allow the flash cell threshold voltage to be placed to an exactvalue, for Multilevel Flash EEPROM cell applications.

For further discussion of a technique for correction of over-erasure offlash EPROM's, please refer to U.S. Pat. No. 5,467,306, entitled METHODOF USING SOURCE BIAS TO INCREASE THRESHOLD VOLTAGES AND/OR TO CORRECTFOR OVER-ERASURE OF FLASH EPROM's, issued to Kaya, et. al.

For many repair processes in the prior art, soft programs areimplemented as bulk operations applied to all erased cells in aparticular memory at the same time. Such bulk operation soft programsconsume currents that are excessive for low power applications.

Another problem arises during repair (or soft program) processing afterthe erase cycle because the soft program cycle is applied to all of theerased cells at the same time, without regard to whether a particularbit line has one or more cells that have been over-erased to a defectivecondition. Defectively over-erased cells can have extremely lowthreshold voltages after several erase cycles. Bit lines containing suchlow threshold voltage cells are considered defective because theyconsume extremely high current during soft programming. Pumping circuitscan be used to provide the data line voltage in a soft program cycle.Because of the limited current capability of such pumping circuits, theinefficiencies caused by the loss of current to over-erased cells areexacerbated when the data line voltage is provided by a pumping circuit.

In any case, the repair and repair verification processes aretime-consuming.

Therefore, a method and device which repairs over-erased cells in FLASHmemory, and other floating gate memory, more quickly and efficiently isneeded.

SUMMARY OF THE INVENTION

One aspect of the invention provides a method for soft programmingsuccessive bit lines in an integrated circuit having floating gatememory cell arrays. The soft programming method is adapted to quicklyand efficiently repair over-erased cells. The soft programming issuitable use in an embedded erase algorithm of other erase sequences forintegrated circuit flash memory devices and for other floating gatememories disposed in integrated circuits. According to the invention,the soft program voltage is applied, on a bit line by bit line basis, tosuccessive subject bit lines within an integrated circuit memory array.The bit line soft programming method is also referred to herein as theBLISP method.

The BLISP method is accomplished in a floating gate integrated circuit.The integrated circuit includes a first memory array having a pluralityof bit lines. The bit lines correspond to floating gate memory cells.The memory cells are configured to be programmed and erased. Each of thecells has a drain, a source, and a control gate. The control gates ofthe cells are in communication with word lines.

The BLISP method includes maintaining the word lines at a predeterminedword line voltage level. The method also includes generating a softprogramming pulse having a soft programming voltage level, selecting aselected bit line, and during the maintaining, applying the softprogramming voltage level to cells disposed on a subject bit linecorresponding to the selected bit line. This basic BLISP method istypically used for memory arrays with zero defective bit lines, in whichcase, the subject bit line comprises the selected bit line.

In some embodiments, the first memory array includes conforming bitlines and defective bit lines and the BLISP method is adapted tologically replace the defective bit lines. The selecting includesindicating a bit line type corresponding to the selected bit line. Theintegrated circuit includes a redundancy system including a secondmemory array and processing resources. The second memory array hasredundant bit lines. The processing resources are adapted to perform theindicating. The bit line types include a conforming bit line type and adefective bit line type. In response to indicating the conforming bitline type, the subject bit line comprises the selected bit line. Inresponse to indicating the defective bit line type, the subject bit linecomprises a subject redundant bit line. The subject redundant bit linelogically replaces the selected bit line.

For the BLISP method adapted to logically replace the defective bitlines, the first memory array can include a plurality of blocks. Each ofthe blocks has at least one bit line. Prior to the soft programming themethod includes erasing cells disposed in conforming bit lines disposedin blocks having set erase flags, and erasing cells disposed in subjectredundant bit lines logically replacing defective bit lines disposed inthe blocks having set erase flags.

For the BLISP method adapted to logically replace the defective bitlines, the applying can include the redundancy system turning off theselected bit line in response to the indicating of the defective bitline type, so that the soft programming voltage level is not applied tocells disposed on the selected bit line. The applying can also includethe redundancy system turning on the subject redundant bit line so thatthe soft programming voltage level is applied to cells disposed on thesubject redundant bit line.

For the BLISP method adapted to logically replace the defective bitlines, the bit lines in the first memory array can have addresses. Theredundancy system processing resources can include a redundancy bit linedecoding system having a first set of cells and a logic array. Each cellin the first set can store a bit line type indication corresponding to apredetermined bit line address. The indicating can include the decodingsystem receiving a bit line address input corresponding to the selectedbit line. The indicating can also include the logic array comparing thebit line address input with the bit line type indication of the bit linecorresponding to the address input. The applying can include respondingto the indicating of the defective bit line type by generating a signalto switch off the soft programming pulse for all of the first memoryarray cells. The signal can also switch on the soft programming pulsefor the subject redundant bit line. The applying can also includeresponding to the indicating of the conforming bit line type bygenerating a signal to switch on the soft programming pulse to theselected bit line.

For some of the embodiments having a first set of cells, the redundancybit line decoding system can include an exclusive NOR gate coupled tothe bit line address input and the corresponding bit line typeindication. The applying can include, responsive to the indicating ofthe defective bit line type, the corresponding exclusive NOR gatetoggling on a coupled redundant bit line enable signal.

In some embodiments, the selected bit lines have corresponding softprogramming flags. The method includes, prior to the maintaining,setting the soft program flags for the selected bit lines. For some ofthe embodiments having soft programming flags, the bit lines in thefirst memory array have addresses. After the applying, the methodincludes determining whether the selected bit line address correspondsto a last address. Responsive to the selected bit line addresscorresponding to the last address, the soft programming flags for theselected bit lines are reset. Responsive to the selected bit lineaddress not corresponding to the last address, the bit line address isincremented and the maintaining, generating, selecting, and applyingsteps are repeated for a next bit line corresponding to the incrementedaddress.

A second aspect of the invention provides a method for correcting anover-erase condition within a non-volatile memory array. The methodincludes providing a first non-volatile memory array in an integratedcircuit. The array has a plurality of memory cells. Each memory cellcomprises a stacked pair of control and floating gates spaced above achannel region interposed between a source and drain region. The memorycells are arranged in bit lines. The method includes selecting aselected bit line. The method also includes applying a first voltage tothe control gate, an active current limiter to the source region, anon-positive voltage to the channel region, and a positive secondvoltage to the drain region of memory cells disposed in a subject bitline corresponding to the selected bit line.

In some embodiments of the second aspect, the subject bit line comprisesthe selected bit line. In some embodiments, the first voltage is betweenminus one volt and six volts.

In some embodiments of the second aspect, the first non-volatile memoryarray includes conforming bit lines and defective bit lines. Theselecting includes indicating a bit line type corresponding to theselected bit line. The integrated circuit includes a redundancy systemincluding a second non-volatile memory array having a plurality ofmemory cells and processing resources. The second non-volatile memoryarray has redundant bit lines. The processing resources are adapted toperform the indicating. The bit line types include a conforming bit linetype and a defective bit line type. In response to indicating theconforming bit line type, the subject bit line comprises the selectedbit line. In response to indicating the defective bit line type, thesecond voltage is not applied to the selected bit line, and the subjectbit line includes a subject redundant bit line logically replacing theselected bit line.

A third aspect of the invention provides an integrated circuit capableof implementing the BLISP method. The integrated circuit comprises afirst memory array, processing resources, word lines, and a controlcircuit. The first memory array has floating gate memory cells disposedon bit lines. Each of the cells in the first memory array has a drain, asource, a floating gate, and a control gate. The processing resourcesare adapted to select selected bit lines for soft programming. The wordlines are in communication with the control gates. The control circuitis coupled with the processing resources to apply a soft program to thefloating gate memory cells disposed on subject bit lines, the subjectbit lines corresponding to selected bit lines.

In some embodiments of the integrated circuit, the subject bit linescomprise the selected bit lines. In some embodiments, the selected bitlines have corresponding soft programming flags; and the control circuitis adapted to set the soft program flags for the selected bit linesprior to the maintaining.

In some embodiments, the integrated circuit includes a state machinecircuit. The first memory array is arranged in blocks of memory cells.Each of the blocks has at least one bit line, and a block erase flagcorresponding to the block. The state machine circuit and the processingresources are coupled to erase, prior to the soft programming, cellsdisposed in the subject bit lines disposed in blocks having set eraseflags. The state machine circuit is adapted to determine whether theselected bit line address corresponds to a last address after theapplying. In response to the selected bit line address corresponding tothe last address, the state machine circuit resets the soft programmingflags. For some of these embodiments, the integrated circuit includes anaddress counter. In response to the selected bit line address notcorresponding to the last address, the address counter increments thebit line address and causes the integrated circuit to repeat the softprogram for a next bit line corresponding to the incremented address.

In some embodiments of the integrated circuit, the control circuit isadapted to maintain the word lines at a predetermined voltage level. Thevoltage level set on the word lines is between approximately aboveground and 0.5 volts. The applying includes applying a soft programpulse to the subject bit lines while maintaining the word line voltage.In some embodiments, the soft programming pulse repairs over-erasedcells so that the over-erased cells may be reprogrammed absent apreviously applied repair verify operation.

In some embodiments of the integrated circuit, the first memory arrayincludes a plurality of blocks, arranged in rows and columns. Each blockincludes the bit lines, the word lines, and source lines. The controlcircuit is coupled to the bit lines, the source lines, and the wordlines. The control circuit is adapted to set threshold voltages of thecells in selected blocks to a low threshold voltage. The control circuitincludes voltage supply circuits to supply a voltage sequence to lowerthe threshold voltages of cells in each selected block. The voltagesequence results in a first group of cells having threshold voltageslowered below a selected limit for the threshold voltage. The voltagesupply circuits supply a soft programming pulse to subject bit linesdisposed in each selected block during a soft programming time intervalacross the source lines and the bit lines, while setting the voltage onthe word lines to a level below the selected limit.

In some embodiments of the integrated circuit, the first memory array isarranged in rows and columns. The integrated circuit includes well linescoupled to wells of respective rows of cells in the first memory array.The control circuit includes voltage supply circuits to supply a wellvoltage on the well lines corresponding to the selected bit lines. Thecontrol circuit couples an active current limiter to the source linescorresponding to the selected bit lines. In some embodiments, theprocessing resources include a soft program repair state machine and anaddress counter.

In some embodiments of the integrated circuit, the first memory arraybit lines comprise defective bit lines and conforming bit lines. Theintegrated circuit includes a redundancy system having a second array offloating gate memory cells disposed on redundant bit lines, andprocessing resources. Each of the cells in the second memory array has adrain, a source, and a control gate. The redundant bit lines logicallyreplace the defective bit lines. The processing resources adapted toindicate bit line types of the selected bit lines in the first memoryarray are disposed in the redundancy system. The subject bit linesinclude selected conforming bit lines and subject redundant bit lineslogically replacing selected defective bit lines. The control circuit isadapted to cooperate with the redundancy system to prevent applying ofthe soft program to floating gate memory cells disposed on defective bitlines.

For some of the embodiments of the integrated circuit having aredundancy system, the applying includes applying a soft program pulse.The bit lines in the first memory array have addresses. The redundancysystem processing resources include a redundancy bit line decodingsystem. The redundancy bit line decoding system includes a first set ofcells, a logic array, and processing resources. Each cell in the firstset of cells stores a bit line type indication corresponding to apredetermined bit line address. The logic array is adapted to compareeach bit line address input with the bit line type indicationcorresponding to the address input. The processing resources are adaptedto receive bit line address inputs corresponding to the selected bitlines. The processing resources respond to a defective bit line typeindication by generating a signal to switch off the soft programmingpulse for the first memory array bit lines. The processing resourcesrespond to a conforming bit line type indication by generating a signalto switch on the soft programming pulse for the selected bit line.

For some of the embodiments of the integrated circuit having aredundancy system, the applying includes applying a soft program pulse.Responsive to an indication of the conforming bit line type, theredundancy system processing resources are adapted to enable applicationof the soft program pulse to the selected bit lines. Responsive to anindication of the defective bit line type, the processing resources areadapted to disable application of the soft program pulse to the selectedbit lines, and enable application of the soft program pulse to thesubject redundant bit lines logically replacing the selected bit lines.

For some of the embodiments of the integrated circuit having aredundancy system, the first memory array is arranged in blocks ofmemory cells. Each of the blocks has at least one bit line, and a blockerase flag corresponding to the block. The control circuit and theredundancy system processing resources are coupled to erase, prior tothe soft programming, cells disposed in the selected conforming bitlines disposed in blocks having set erase flags. The control circuit andthe redundancy system processing resources are also coupled to erase,prior to the soft programming, cells disposed in the subject redundantbit lines logically replacing defective bit lines, the defective bitlines disposed in blocks having set erase flags.

For some of the embodiments of the integrated circuit having aredundancy system, the first memory array and the second memory arrayare arranged in rows and columns. The integrated circuit includes welllines coupled to wells of respective rows of cells in the first memoryarray and coupled to respective rows of cells in the second memoryarray. The control circuit voltage supply circuits supply a well voltageon the well lines corresponding to the selected bit lines. The controlcircuit couples an active current limiter to the source linescorresponding to the selected bit lines.

For some of the embodiments of the integrated circuit having aredundancy system, the applying includes applying a soft program pulse.The redundancy system processing resources include a redundancy bit linedecoding system having a first set of cells. Each cell in the first setstores a bit line type indication corresponding to a predetermined bitline address. The redundancy bit line decoding system also has a logicarray. The logic array is adapted to compare each bit line address inputwith the bit line type indication corresponding to the address input.The redundancy bit line decoding system also has processing resourcesadapted to receive bit line address inputs corresponding to the selectedbit lines.

The redundancy bit line decoding system processing resources are adaptedto respond to a defective bit line type indication by generating asignal to switch off the soft programming pulse for the first memoryarray bit lines, and to switch on the soft programming pulse for thesubject redundant bit line. The redundancy bit line decoding systemprocessing resources are adapted to respond to a conforming bit linetype indication by generating a signal to switch on the soft programmingpulse to the selected bit line. The redundancy bit line decoding systemcan include exclusive NOR gates coupled to the bit line address inputsand the corresponding bit line type indications. Responsive to defectiveselected bit line type indications, the exclusive NOR gates are adaptedto toggle on the coupled redundant bit line enable signals.

A fourth aspect of the invention provides a floating gate memorycomprising floating gate cells, a first circuit, and a second circuit.The floating gate cell have a drain, a control gate, a floating gate, awell, and a source. The floating gate cells are disposed on bit lines ina first memory array. The first circuit is adapted to select selectedbit lines. The second circuit is adapted to soft program floating gatecells in subject bit lines. The subject bit lines correspond to theselected bit lines. The second circuit is also adapted to supply a gatevoltage to the control gate, an active current limiter to the drain, awell voltage to the well, and a source voltage to the source of thefloating gate cells in the subject bit lines.

For some of the embodiments, the memory includes floating gate cellshaving a drain, a control gate, a floating gate, a well, and a source.The floating gate cells are disposed on bit lines in a second memoryarray. The second circuit is adapted to supply a gate voltage to thecontrol gate, an active current limiter to the drain, a well voltage tothe well, and a source voltage to the source of the cells in the secondmemory array. The subject floating gate cells are also disposed onredundant bit lines. The redundant bit lines disposed in the secondmemory array. The redundant bit lines logically replacing defective bitlines in the first memory array.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1A is a schematic diagram providing an overview of an integratedcircuit embodiment according to the invention for substrate currentinduced hot electron injection (SCIHE) approach for threshold voltageconvergence at low V_(CC) voltage.

FIG. 1B is a schematic diagram providing an overview of an integratedcircuit embodiment adapted to logically replace defective bit lines.

FIG. 2A is a circuit diagram showing a segmented array architecture fora floating gate memory cell device in which the SCIHE approach can beimplemented.

FIG. 2B is a circuit diagram showing a segmented array architectureincluding a common well line, and a current limiter in which the SCIHEapproach can be implemented.

FIG. 2C is a circuit diagram showing a generalized segmented arrayarchitecture in which the BLISP method can be implemented.

FIG. 3A is a flow chart showing a method for chip, block, or bit lineerase process with soft programming steps according to the SCIHEapproach.

FIG. 3B is a flow chart showing a method for chip, block or bit lineerase process with general soft programming steps.

FIG. 4 is a circuit diagram of a floating gate memory cell with biasvoltages and current sink.

FIG. 5 is a diagram of a floating gate memory cell and a currentlimiter.

FIG. 6 is a flow chart illustrating a two-stage soft programmingprocess.

FIG. 7 is a timing diagram of a programming sequence.

FIG. 8A is a flow diagram illustrating the bit line soft program (BLISP)method.

FIG. 8B is a flow diagram illustrating the bit line soft program (BLISP)method adapted to logically replace defective bit lines.

FIG. 8C is a flow chart of a block erase process including the BLISPmethod.

FIG. 9A is a schematic circuit diagram illustrating a bit line addressdecoding system connected to address inputs.

FIG. 9B is a schematic circuit diagram illustrating the redundancy bitline address decoding circuit disposed in a redundancy system.

FIG. 9C is a schematic circuit diagram illustrating the connection ofthe bit line decode signals to the first cell array and the secondmemory array.

DETAILED DESCRIPTION

A detailed description of preferred embodiments of this invention isprovided with reference to the figures. The soft program of thisinvention may be part of an embedded erase sequence of a floating gatememory cell device, where such a device includes an array of cellsarranged in blocks. The soft program generates pulses for quicklyrepairing over-erased cells on a bit line by bit line basis, whilelimiting the amount of current generated during the process. For memoryarrays with no defective memory cells, the invention provides anefficient repair method that is capable of operating at low currentscompared to bulk operations because the number of erased cells to whichthe soft program pulse is simultaneously applies is much lower for thebit line by bit line method.

For some memory arrays, certain defects render some of the bit linestherein unusable or “defective”. The number of defective bit linesbecomes especially problematic for high density memory arrays. Theusable bit lines are referred to herein as “conforming”.

The bit line defects can be the result of the fabrication process,including defective memory cells in the bit line, bit line to bit linemetal shorts, bit line metal opens, bit line leakage, and otherelectrical defects. There is no apparent benefit to subjecting bit lineshaving defects other than those related to floating gate charging, toerase, program and soft program cycles, because regardless of the cellconditions, such defective bit lines will remain unusable. Also, thedefects for such bit lines will likely result in the inability of theerase, program and soft program cycles to have their intended effects onthe cells disposed in the bit lines.

Over-erased cells require greater electron injection and higher draincurrent during the soft program cycle. The higher soft programming draincurrent requirements for bit lines having cells that are substantiallyover-erased limit the soft programming efficiency. The high draincurrent for the over-erased cells can create voltage spikes during thesoft programming. The voltage spikes result from the integratedcircuit's inability to sustain a sufficiently high data line voltage.The higher drain currents also arise because the defective memory cellsare unable to converge to within the proper threshold voltage range. Thegreater electron injection requirement for the low threshold voltagecells in the defective bit lines results in: (1) greater soft programcycle times for the defective bit lines, (2) more time-outs and cyclerepeats if the soft program algorithm is subject to time out criteria,and/or (3) higher drain line current requirements during softprogramming.

Substrate Current Induced Hot Electron Injection (SCIHE) Approach forV_(T) Convergence at Low V_(CC) Voltage

During soft programming, a gate voltage is supplied to the control gate,a drain voltage is supplied to the drain, a well voltage is supplied tothe well, and an active current limiter is coupled to the source.Embodiments of the invention have the advantage that usable electronsflowing from the current source are conducted to cells having lowerV_(T), where cell conductance is much higher, increasing soft programefficiency. The SCIHE invention is described by patent application Ser.No. 08/926,554, entitled METHOD AND CIRCUIT FOR SUBSTRATE CURRENTINDUCED HOT INJECTION (SCIHE) APPROACH FOR V_(T) CONVERGENCE AT LOWV_(CC) VOLTAGE, filed Sep. 10, 1997, which is incorporated herein byreference.

The use of the active current limiter coupled to the source hasadvantages over approaches that use a ground or a constant voltagesource coupled to the source or approaches that use a diode connection.The active current limiter also has advantages over approaches where asource bias is established by a diode connection, a series resistance,or feedback circuitry monitoring the flash cell's drain and gate. Unlikevarious prior approaches, using the active current limiter has anadvantage of helping to keep electron flow constant.

FIG. 1A shows the basic structure of a floating gate memory cellintegrated circuit incorporating an embodiment of the SCIHE invention.The SCIHE integrated circuit 100 includes a first memory array,generally 110, which is divided into a plurality of blocks (32 blocks inthe figure). Each block has a unique address for reading, programming,preprogramming, erasing and soft programming processes. The segmentedarchitecture of the first memory array 110 allows application of therepair pulse of this invention to blocks of memory cells individually,thus allowing block by block repair of over-erased cells. Thearchitecture of the first memory array 110 is described in detail belowwith reference to FIG. 2A that illustrates a segmented arrayarchitecture for the SCIHE approach 200A. The segmented arrayarchitecture for the SCIHE approach 200A is shown in a drain sourcedrain configuration of a floating gate memory circuit including aportion of the first memory array 110. The discussion of FIG. 1B isprovided in the Bit Line Soft Programming Method section below.

Still referring to FIG. 1A, coupled with the first memory array 110 area voltage bias/active current limiter, generally 160, and a read/programcontrol/block erase/erase verify/ repair circuit, generally 120. Voltagebias/active current limiter 160 provides enhanced efficiency during softprogramming. The read/program control/block erase/erase verify/repaircircuit 120 is coupled to block erase flags 130. An address counter 140is included for incrementing through memory cells, blocks, bit lines orthe entire array for the erase/erase verify/repair sequence. Repair isalso referred to as “soft program” herein.

The chip includes command logic 150 that is coupled to the address,data, and other control lines such as the output enable and chip enablesignals. The command logic 150 interprets inputs to set a mode ofoperation for the voltage bias/active current limiter 160 and theread/program control/block erase/erase verify/repair circuit 120.

Command logic 150 may be implemented as done in standard floating gatememory integrated circuits, such as the Am28F020 flash memory chipmanufactured by Advanced Micro Devices, Inc. of Sunnyvale, Californiawith additional commands of this invention for cell, block, bit line orarray erase. In response to commands issued by the command logic 150, anembedded erase operation is executed by state machines in theread/program control/block erase/erase verify/repair circuit 120. Theuser, through a host CPU or otherwise, supplies address and data signalsto the command logic 150 to indicate a preferred mode of operation. Themodes executed by read/program control/block erase/erase verify/repaircircuit 120 include a chip erase mode in which all blocks in the firstmemory array 110 are to be erased and a block erase mode in whichselected blocks in the first memory array 110 are to be erased. Inresponse to user input, blocks to be erased are identified by block orsector erase flags 130 stored on the chip. FIG. 2A illustrates thedetails of a segmented array architecture in a drain-source-drainconfiguration of the floating gate memory circuit in which thisinvention may be implemented, and like that described U.S. Pat. No.5,399,891, entitled NON-VOLATILE MEMORY CELL AND ARRAY ARCHITECTURE,issued Mar. 21, 1995 which is incorporated by reference herein. Otherarray architectures may be used, as well.

The circuit includes a first local bit line 203 and a second local bitline 206 that are implemented by buried diffusion conductors. Also,included is a common source connection line 209 implemented by burieddiffusion. A plurality of floating gate transistors have drains andsources coupled to the local bit lines 203, 206, and common sourceconnection line 209. Any number of these floating gate transistors in asingle block may suffer from over-erasure as a result of the erase stepmentioned above, and in varying degrees.

The drains of the first column of transistors, generally 212, arecoupled to the first local bit line 203, and the drains of the secondcolumn of transistors, generally 215, are coupled to the second localbit line 206. The gates of the floating gate transistors are coupled toword lines WL₀ through WL_(N), where each word line (e.g., WL₁) iscoupled to the gate of a transistor (e.g., transistor 218) in the firstlocal bit line 203 and a transistor (e.g., transistor 221) in the secondlocal bit line 206. The transistors 218 and 221 can be considered a twotransistor cell with a shared source diffusion.

The act of charging the floating gate is called the program step for thefloating gate memory cell. This is accomplished on a byte by byte basisthrough hot electron injection by establishing a large positive voltagebetween the gate and the source, such as twelve volts, and a positivevoltage between the drain and the source, such as six volts.

The act of discharging the floating gate is called the erase step forthe floating gate memory cell. This is accomplished through the F-N(Fowler-Nordheim) tunneling mechanism between the floating gate and thesource (source erase) or between the floating gate and the substrate(channel erase). The source erasing is performed by applying a positivebias to the source, such as twelve volts or seven volts, while the gateis grounded or negatively biased, such as minus seven volts. The channelerasing on a block basis is performed by applying a negative bias to thegate and/or a positive bias to the substrate.

Individual blocks of cells are controlled by select signals, that is,top block select signals TBSEL_(A) and TBSEL_(B) and bottom block selectsignals BBSEL_(A) and BBSEL_(B). The individual control of the blocksprovides the ability to apply a repair pulse to selected local bit lines203 and 206.

Still referring to FIG. 2A, a first global bit line 224 and a secondglobal bit line 227 are associated with each drain-source-drain block.The first global bit line 224 is coupled to the source of top blockselect transistor 230 through a metal-to-diffusion contact 269.Similarly, the second global bit line 227 is coupled to the source oftop block select transistor 233 through a metal-to-diffusion contact272. The drains of the top block select transistors 230, 233 are coupledto the first and second local bit lines 203 and 206, respectively. Thegates of the top block selector transistors 230, 233 are thus controlledby a top block select signal TBSEL_(A) on line 236.

In a similar manner, the gate of the transistor 285 is controlled by abottom block select signal BBSEL_(A) across line 242. The local commonsource connection line 209 is coupled to a terminal across conductor 263through transistor 285. The drain of the transistor 285 is coupled tothe common source connection line 209. The source of the transistor 285is coupled to the conductor 263. In this architecture, the conductor 263is a buried diffusion conductor which extends to a metal-to-diffusioncontact 281 at a position displaced horizontally through the array. Themetal-to-diffusion contact 281 provides contact to a vertical metal bus239.

For sense amplifiers and program data in structures, a data line 245 iscoupled to the global bit lines 224 and 227 which extend verticallythrough the array to respective column (or global bit line) selecttransistors 293, 294. Thus, the source of column select transistor 293is coupled to global bit line 224, the gate of column select transistor293 is coupled to a column (or global bit line) decode signal Y_(n0),and the drain of the column select transistor 293 is coupled to dataline conductor 245.

The blocks of floating gate memory cells as shown in FIGS. 1A and 1B areconfigured into a plurality of sub-arrays as illustrated in FIG. 2Awhich illustrates two sub-arrays within a larger integrated circuit. Thesub-arrays represent a physical layout segmentation of the memory array.The sub-arrays are divided generally along dotted line 248 and includesub-array 251 generally above the line 248 and sub-array 254 generallybelow the line 248. A first group 257 of cells is laid out in a mirrorimage with a second group 260 of cells along a given bit line pair(e.g., 224, 227). As one proceeds up the bit line pair, the memorysub-arrays are flipped so as to share conductors 263, 266 (burieddiffusion) and metal-to-metal diffusion contacts 269, 272, 275, 278. Theconductors 263, 266 extend horizontally across the array to a verticalmetal line 239 through metal-to-diffusion contacts 281, 284. Thesub-arrays repeat on opposite sides of the metal bus 239 so thatadjacent sub-arrays share a metal bus 239. The metal bus 239 is coupledto array ground and erase high voltage circuitry. Thus, the sub-arraylayout requires two metal contact pitches per column of two transistorcells for the global bit lines and one metal contact pitch for the metalbus 239.

Floating gate memory cells include wells 296A-296L. Well lines 295A-295Care shown in FIG. 2. Well lines 295A-295C are for applying bias voltagesto wells 296A-296L. Well line 295A is coupled to wells 296A through296D. Well line 295B is coupled to wells 296E through 296H. Well line295C is coupled to wells 2961 through 296L.

During a soft program pulse, a gate voltage is applied to gates of thefloating gate cells via the word lines (WL_(0−n)), a drain voltage isapplied via bit lines 224 and 227, a well bias is applied via the welllines 295A-295C, and an active current limiter is applied to the sourcesvia a structure including transistors 285-288 and the additionalcircuitry shown in FIG. 5, which forms a current mirror. In such anarchitecture, the transistors 285-288 of FIG. 2A each correspond to atransistor such as the transistor 516 shown in FIG. 5. BBSEL_(A) andBBSEL_(B) each correspond to the line V_(CS) in FIG. 5, which is coupledto the gate of transistor 516. Not shown in FIG. 2A are additional welllines for the other floating gates shown in FIG. 2A. However, additionalwell lines are used to apply well bias voltages to the other wells.Transistors 285, 286, 287, and 288 are also selector decode transistors.These transistors on their source sides are connected to a generator tosupport 0 volts or a positive voltage depending on the mode ofoperation.

In this approach, using an active current limiter rather than groundingthe source, the power of the pumping circuitry can be better utilized toprogram the over-erased cells and decrease the leakage current from mostof the cells by orders in magnitude. In an alternative system, the gatevoltage can be stepped to decrease the current contribution from theover-erased cells.

The sector decode ability provided by the circuit of FIG. 2A, allows thecircuitry to be implemented which applies a drain disturb style softprogram pulse only to selected segments of the array by applying about 4volts to the local drain lines, while coupling the source to an activecurrent limiter.

Also, an alternative system will apply the soft program pulse of about 4volts, or more depending on circuit parameters, through the sourceterminal of devices being soft programmed, while coupling the bit linesor drain terminals to an active current limiter. The same block-by-blockdecoding, and word line drivers can be utilized in this source disturbapproach.

FIG. 2B is a circuit diagram showing a segmented array architectureincluding a common well line 297, and an active current limiter 299 inwhich the SCIHE approach can be implemented 200B and is similar to FIG.2A. The common well line 297 allows application of a well voltage tomultiple cells. Instead of transistors 285-288, FIG. 2B includes switch298 and an active current limiter 299. The active current limiter 299 iscoupled to a metal bus 239 via a switch 298. The active current limiter299 provides a current sink commonly to multiple cells throughout thearray. See the Bit Line Soft Program Method section below for thediscussion of FIG. 2C.

Referring to FIG. 3A, an overall flow charts of a chip or block eraseprocess, including the soft program steps of an embodiment of the SCIHEinvention, is shown. FIG. 3B shows the same flowchart as FIG. 3A, exceptthat the soft program in FIG. 3B does not require the inclusion of SCIHEinvention features such as the active current limiter, or the wellswitch discussed below with reference to FIG. 4. The bit line by bitline soft program method can be utilized with the soft program settingsas shown in either FIG. 3A or FIG. 3B. After starting the eraseoperation (step 305), pre-programming is initiated for the chip or blockselected for erase, through a host CPU or otherwise through commandlogic 150 (step 310). At step 315, a pre-program recovery period occursallowing the voltage to settle out or stabilize after pre-programming.At step 320, a pre-program verify process occurs. The system then checksto see if the last address in the chip, block or bit line has beenpre-programmed (step 325). If not, the process starting at thepre-programming step 310 is repeated until all cells in the chip, blockor bit line have been preprogrammed.

After pre-programming, the erase operation at step 330 is executed. Theerase step 330 is followed by the erase recovery period 335 to allow theerase voltage to settle out. Next, an erase verify operation 340 isperformed. Then, the system checks to see if the erase process iscomplete at step 345. If not, it returns to perform the erase operation330 until the erase operation 330 is complete.

When the erase operation is complete, the SCIHE soft program at step 350is initiated according to the SCIHE process shown in FIG. 3A, in whichthe soft program pulse is applied to all cells in the entire chip, orthe block or bit line subject of the erase operation in parallel. Thesoft program step 350 includes applying a gate voltage to the gates, adrain voltage to the drains, a well voltage to the wells, and a constantsource current to the sources.

A generalized soft program step 352 is provided in FIG. 3B. Thegeneralized soft program 352 does not necessarily include SCIHE featuressuch as the active current limiter, or the well switch. For both softprograms, a soft program recovery occurs at step 355. The process endsat step 360.

FIG. 4 shows a floating gate memory cell configured for soft programmingaccording to an embodiment of the SCIHE invention. The floating gatememory cell 400 includes a control gate 401, a floating gate 402 underthe control gate, a source 403, a well 404, and a drain 405. Thefloating gate memory cell 400 comprises a control gate 401 and afloating gate 402 from a stacked pair of polysilicon layers having adielectric layer interposed between them. The gate switch 410 is coupledto the control gate 401 and provides a control gate voltage ofapproximately 2 volts. The source switch 411 is coupled to the source403 and provides an active current limiter 420 to the source 403. Thewell switch 412 is coupled to the well 404 and provides a well biasvoltage of approximately 2 volts to the well 404. A drain switch 413 iscoupled to the drain 405 and provides a drain voltage of approximately 4volts to the drain 405.

The configuration shown in FIG. 4 allows for soft programming of thefloating gate memory cell 400. The soft programming causes hot electroninjection of electrons onto the floating gate. In one embodiment of theinvention the length (L_(mask)) of a cell is 0.6 micrometers, and thewidth (W_(mask)) is 0.4 micrometers. The tunnel oxide is 10 nanometers,and the oxide nitrite oxide (ONO) layer is approximately 14 nanometers.The floating gate memory cell 400 is an n-channel transistor.

A triple well architecture is used for a cell. The triple well structureincludes a deep N-well, a P-well, and an N-well. If the P-well is keptgrounded, a twin well structure can be used. The P-well acts as achannel well and the deep N-well acts as the isolation well. During softprogramming, the channel well can be biased to an non-positive voltage,while the isolation well is kept equal to or larger than Vcc.

An advantage of use of an active current limiter is that usableelectrons flowing from the source are conducted to lower V_(T) bitswhere the cell conductance is much higher. Therefore, the soft programefficiency will be greater. The conductance modulation is through thecharged source voltage and may be proportional to log₁₀{-[V_(S)+_(G)V_(T)(V_(SB))]/110 mV}, where _(G) is the gate couplingratio. The active current limiter 420 applies a negative constantcurrent to the source. The configuration shown has the additionalbenefit that the drain current could be supplied directly from V_(CC)=5volts, which may be larger than the current available from chargepumping circuitry. If V_(CC) is lowered, the relative voltage can bechanged accordingly. The use of a negative well bias will requireanother pumping circuit. If a positive pump circuit is used for thedrain voltage, then the negative pump circuitry will not be needed. Thedifference between the drain voltage and the well bias voltage isimportant.

A fast V_(T) convergence is desirable. The longer the soft program time,the tighter the V_(T) convergence. The upper limit is the total sectorelectrical erase time. Initially bits (cells) will have a wider V_(T)distribution, and the initial source voltage will be high. Optionally, astepped or ramped word line voltage (gate voltage) may be used to changethe drain to source voltage margin. The voltage between gate and sourcewill affect the saturated value of converged V_(T).

Since the soft program current is also suppressed through theV_(T)(V_(SB)) from body effect, the higher impurity concentration of asubstrate is helpful. The high impurity concentration of the substratewill suppress the short channel effect and its related leakage. Thedrain coupling ratio, which may affect the leakage, may also be reduced.The drain coupling is a capacitance coupling effect from the N+ floatinggate overlap.

More details regarding methods of soft programming floating gates aredescribed in U.S. Pat. No. 5,745,410 entitled METHOD AND SYSTEM FOR SOFTPROGRAMMING ALGORITHM, issued Apr. 28, 1998, which is incorporatedherein by reference.

FIG. 5 is a diagram of a memory cell and an active current limiteraccording to an embodiment of the present SCIHE invention. The currentlimiter circuit 500 corresponds to active current limiter 420 of FIG. 4.The current limiter switch includes transistor 510 coupled to V_(CC) andV_(load), resistor 512, transistor 514, and transistor 516. I_(out) iscoupled to source switch 411. V_(load) is used to control the currentfrom I_(ouut). I_(out) is coupled to array V_(SS) 520, which is coupledto sources of memory cells including memory cell 522. Also shown in FIG.5 are word line 526, array well 524, and drain line 528. With theconfiguration shown in FIG. 5, current is limited from the sources ofmemory cells in an array of memory cells.

A block of memory cells may be programmed simultaneously. To program ablock of 512K cells simultaneously, the current limiter circuit 500 isconstructed to cause the total current through the current limitercircuit 500 to be approximately 2 milliamperes for the block. In analternative embodiment, the current for the 512K cell block may be lessthan 10 milliamperes (mA).

Turning to FIG. 6, another embodiment of the SCIHE invention is shown.Optionally, as shown here, the repair pulse may be applied in twosequential steps. In the first step, the word line voltage is maintainedat a first level about ground, and in the second step, the word linevoltage is maintained at a second level about ground. FIG. 6 shows thatduring steps 607 through 610, the word line voltage is maintained at twodifferent levels while the repair pulse is applied to the bit line.

First, step 607 provides that the word line voltage is maintained aboveground, e.g. between 0.1 volts and 0.2 volts, for a period of time, e.g.approximately 100 milliseconds. The first stage of the repair pulse ismaintained during step 608. By first applying a lower word line biasduring the first soft program steps 607 and 608, the current of the“over-erased” cells is less than would occur with higher word linevoltage, yet a majority of the over-erased cells are pushed toward being“normal cells” (i.e. they recover the threshold voltage to a bettervalue). Thus, after the first soft program steps 607 and 608, someover-erased cells have been recovered and the second step can beapplied. The second steps 609 and 610 include setting the word linevoltage to about 0.6 volts, which is applied for an additional period oftime, e.g. approximately 100 milliseconds while the repair pulse isapplied.

Accordingly, during the repair pulse, the word line voltage is driven intwo stages, the first stage occurring during the 100 milliseconds periodwhile the word line voltage is maintained between approximately 0.1volts and 0.2 volts, the second stage occurring during the 100milliseconds period while the word line voltage is maintained at about0.6 volts. This two-step process enhances the soft programming of theover-erased cells with less operating current and better operatingefficiency.

The following table shows alternative values for a two-step softprogramming process:

3 V Technology Source I_(S) for a 512K Drain Gate cell block SubstrateTime 1^(st) step +5.5 V +2.5 V 1.5 mA GND  50 ms 2^(nd) step +5.5 V +3.1V 1.5 mA GND 100 ms

5 V Technology Source I_(S) for a 512K Drain Gate cell block SubstrateTime 1^(st) step V_(cc) 0 V 1.2 mA GND 50 ms 2^(nd) step V_(cc) 0.6 V1.2 mA GND 50 ms

The following shows voltage and current ranges for soft programming:

Drain Gate Source Substrate <Drain Junction V_(GS) >−1 V I_(S)/512Kcells <10 ≦0 V mA Breakdown Voltage V_(DG) >2 V VSB >0.5 V V_(DB) <8 V

Accordingly, the method and circuit for substrate current induced hot einjection for V_(T) convergence at low V_(CC) voltage have beenprovided. The method and circuit provide quicker and more efficientrepairing of over-erased cells in a flash memory.

FIG. 7 is a timing diagram of one embodiment of a programming sequence.Voltage is applied to drain as shown by trace 700. A changing voltage isapplied to the word line during programming as shown by trace 702. Thedrain and gate voltage may be applied simultaneously at each step, orthe gate voltage may be applied first.

Bit Line Soft Programming Method

One aspect of the invention is a method for soft programming successivebit lines in an integrated circuit having floating gate memory cellarrays. The method can be performed in an integrated circuit similar toa SCIHE integrated circuit 100 shown in FIG. 1A, or in any floating gatememory integrated circuit that provides bit line selection capability.

The integrated circuit includes a first memory array 110 having aplurality of bit lines. The bit lines correspond to floating gate memorycells. The memory cells are configured to be programmed and erased. Eachof the cells has a drain, a source, and a control gate. The controlgates of the cells are in communication with word lines. For memoryarrays with no defective bit lines, the bit line soft program (BLISP)method 800, as shown in FIG. 8A, and described below is used.

FIGS. 2A, 2B and 2C illustrate the details of segmented arrayarchitectures in a drain-source-drain configuration in which the BLISPmethod 800 may be implemented. These architectures illustrate differentembodiments of the first memory array 110. FIG. 2C shows a generalizedsegmented array architecture in which the BLISP method 800 can beimplemented 200C. The generalized segmented array architecture in whichthe BLISP method 800 can be implemented 200C does not incorporate theSCIHE invention soft program features. The BLISP method 800 can beimplemented in any floating gate memory array that provides column (orbit line) decode signals (such as Y_(n0) through Y_(nM)) correspondingto each bit line. The bit line soft program method 800 does not requirethe block segmented architecture illustrated in FIGS. 2A, 2B and 2C.

As shown in FIG. 2C, the first memory array 110 includes a plurality ofbit lines including the first local bit line 203 and the second localbit line 206. As shown in FIG. 2C, the local bit lines, such as thefirst local bit line 203 and the second local bit line 206, are coupledto drain terminals of floating gate memory cells in the first memoryarray 110. Each of the floating gate memory cells has a drain, a source,and a control gate. The control gates of the cells are in communicationwith word lines, shown in FIG. 2C as the word lines WL_(o) throughWL_(N).

As shown in FIG. 8A, the bit line soft programming (BLISP) method 800for floating gate memory cells includes setting up and maintaining 807the word lines at a predetermined word line voltage level. In someembodiments, the predetermined word line voltage level is betweenapproximately above ground and 0.5 volts.

The BLISP method continues by generating 809 a soft programming pulsehaving a soft programming voltage level, selecting 811 a selected bitline, and applying 813 the soft programming voltage level, or pulse, toa subject bit line. The subject bit line corresponds to the selected bitline. The soft programming voltage level is applied to cells disposed onthe subject bit line.

The BLISP method includes a soft program recovery 815, that typicallyoccurs directly after the applying 813 of the soft program pulse to thesubject bit line. The soft program recovery provides the time needed tofor the selected bit line to recover from the soft program voltage(which is approximately five to six volts for some embodiments of theinvention) to the normal standby voltage condition of approximately zerovolts for some embodiments of the invention. The soft program recoveryalso provides the time needed for the word lines to recover back fromthe two-step voltage application to zero volts. Therefore, after thesoft program recovery 815, the word lines and the bit lines are settledback to their respective normal standby conditions.

The BLISP method 800 is adapted to consume substantially less power andcurrent than the prior art bulk operations because the number of erasedcells to which the soft program pulse is simultaneously applied is muchlower for the bit line by bit line method. In some embodiments, thesubject bit line comprises the selected bit line.

Typically, circuits implementing bulk operation soft program methodsrequire direct application of a power line to supply the required highcurrent, e.g., 10 to 90 milliamperes of current driving ability. On theother hand, for low power applications, current consumption exceeding 10milliamperes is not allowed. Low power applications typically have lowvoltage, and direct application of the voltage does not provide thecurrent level needed for bulk soft programming. Therefore, a pumpinggenerator is required to provide the high voltage. However, the pumpgenerators are characterized by intrinsically limited current suppliesthat are usually only a few milliamperes.

In some embodiments of the BLISP method 800, the first memory array 110includes a plurality of blocks, as shown in FIGS. 1A and 1B. Each blockhas at least one bit line. Prior to the soft programming, the methodincludes erasing cells disposed in the bit lines disposed in blockshaving set erase flags. In some embodiments, the soft programming pulserepairs over-erased cells so that the over-erased cells may bereprogrammed absent a previously applied repair verify operation. Therepair verify operation can be omitted, for example, when theover-erased cells are well-characterized by prior testing andevaluation.

In some embodiments, the bit lines in the first memory array 110 haveaddresses. The integrated circuit includes processing resourcesincluding a redundancy bit line decoding system, such as the bit lineaddress decoding system 915 shown in FIG. 9B. The selecting includes theredundancy bit line decoding system 915 receiving a bit line addressinput corresponding to the selected bit line. The applying includes theprocessing resources providing a signal to switch on the soft programpulse to the selected bit line. In one embodiment, the bit line addressdecoding system 910 output is logically combined with a second inputsignal for the redundancy bit line decoding 950, to generate theappropriate bit line decode signal, such as the Y_(n0) signal 960-0 forthe zero bit line in the first memory array 110, to switch on the softprogram pulse to the subject bit line.

For high-density memory products having significant yield reductionsfrom defective bit lines in a memory array, a redundancy system 170 canbe utilized to enhance production yield. The defective bit lines areunusable and can be the result of the fabrication process as describedabove. The redundancy system 170, details of which are shown in FIGS. 9Band 9C, includes a second memory array 905 (see FIG. 9C) and processingresources. The bit lines in the second memory array 905 logicallyreplace defective bit lines in the first memory array 110.

The inclusion of a redundancy system 170 in the integrated circuit isbased on a trade off between the higher yield and the die sizeenlargement attributable to the redundancy system. For example, when thedie size enlargement for the redundancy system 170 is relatively smalland the yield improvement provided by use of the redundancy system iscritically important, the appropriate product strategy is to include theredundancy system 170 in the integrated circuit.

For circumstances where the trade off favors an integrated circuitwithout additional processing resources to logically replace defectivebit lines in the memory array, the redundancy system 170 is not includedand the “basic” BLISP method 800 shown in FIG. 8A is used. For example,a first memory array 110 having no defective bit lines does not requirea redundancy system 170. Similarly for certain integrated circuitshaving a first memory array 110 with a very low number of defective bitlines, the integrated circuit processing resources can ensure that thedefective bit lines do not prevent the floating gate array fromproviding adequate functionality, without the inclusion of a redundancysystem. For example, the integrated circuit can have processingresources, including an address counter and control unit that enable thememory to bypass a limited number of defective bit lines and thereforeoperate effectively despite the presence of such defective bit lines.The first memory array 110 for such an integrated circuit can haveexcess bit lines to enable replacement of the defective bit lines, orthe operations performed by the first memory array can be performed evenwith the presence of a small number of defective bit lines.

The key difference between an integrated circuit having no more than avery low number of defective bit lines and an integrated circuit adaptedto bypass defective bit lines 105 is that the latter has a redundancysystem 170, as shown for one embodiment of the integrated circuitadapted to bypass defective bit lines in FIG. 1B. Another differencebetween the embodiment shown in FIG. 1B and the integrated circuitaccording to the SCIHE approach 100 is that the embodiment shown in FIG.1B has a read and program control circuit that is separate from theblock erase/erase verify/soft program circuit 125, instead of having aread/program control/block erase/erase verify/soft program circuit 120that combines these functions. The read and program control circuit isalso referred to herein as the control circuit 165. A third differenceis that the SCIHE integrated circuit 100 has a voltage bias and anactive current limiter 160. These elements are not required for theintegrated circuit adapted to logically replace defective bit lines 105.

For the integrated circuit adapted to logically replace defective bitlines 105, the first memory array 110 is coupled with the read andprogram control circuit 165 and the block erase/erase verify/softprogram circuit 125. The redundancy system 170 is also coupled with theread and program control circuit 165 and the block erase/eraseverify/soft program circuit 125.

For integrated circuits having a larger number of defective bit lines,the redundancy system 170 is used by the BLISP method adapted tologically replace defective bit lines 801, as shown in FIG. 8B. Thesecond memory array 905 has redundant bit lines. For such integratedcircuits, the BLISP method adapted to logically replace defective bitlines 801 includes providing 822 the redundancy system 170. The BLISPmethod adapted to logically replace defective bit lines 801 alsoincludes maintaining 807 the word lines at a predetermined word linevoltage level, generating 809 a soft programming pulse having a softprogramming voltage level, selecting 811 a selected bit line, andapplying 813 the soft programming voltage level to a subject bit line.

For the BLISP method adapted to logically replace defective bit lines801, the first memory array 110 includes two types of bit lines;defective bit lines and conforming bit lines. In some embodiments, atleast one cell disposed on each of the defective bit lines remains belowa targeted threshold voltage level after a first number of programmingcycles. Therefore, the defective bit line is unusable. For example,referring to FIGS. 2A through 2C, if the second transistor 221, disposedin the second column of transistors 215, remains below a targetedthreshold voltage after a first number of programming cycles, then thesecond global bit line 227 would be considered a defective bit line. Thebelow target value threshold voltages of the cells in the defective bitlines contribute to over-erasing thereof when the cells are subject torepeated programming, erase, and soft programming cycles. In someembodiments, the first number of programming cycles is greater than two.

The second memory array 905 has redundant bit lines with floating gatememory cells that are configured to be programmed and erased. Theredundancy system 170 includes processing resources and provides a bitline selection capability. The second memory array 905 can be coupledwith the address counter 140 and the control circuit (reference number165 in FIG. 1B and hereinafter in this application, and reference number120 in FIG. 1A) to provide bit line addressing and selection. Theselecting 811 of the selected bit line includes indicating a bit linetype corresponding to the selected bit line. The processing resourcesdisposed in the redundancy system 170 are adapted to perform theindicating. The bit line types include a conforming bit line type and adefective bit line type. In response to indicating the conforming bitline type, the subject bit line comprises the selected bit line. Inresponse to indicating the defective bit line type, the subject bit linecomprises a subject redundant bit line. The subject redundant bit linelogically replaces the selected bit line.

For the example introduced above, where the second global bit line 227is a defective bit line, when the selected bit line is the second globalbit line, the selecting 811 of the selected bit line can include theredundancy system 170 processing resources indicating that the selectedbit line is a defective bit line. The subject bit line will be aredundant bit line in the second memory array 905 that logicallyreplaces the second global bit line 227.

On the other hand, the first global bit line 224 can be a conforming bitline. When the selected bit line is the conforming first global bit line224, the selecting 811 of the selected bit line can include theredundancy system 170 processing resources indicating that the selectedbit line is a conforming bit line. The subject bit line will be thefirst global bit line 224.

The applying 813 of the soft programming voltage level is to cellsdisposed on the subject bit line. Responsive to an indication of aconforming selected bit line the soft program pulse is applied to theselected bit line in the first memory array 110. Applying 813 of thesoft programming voltage level occurs while the word line voltage ismaintained 807.

In some embodiments of the, at least one of the defective bit linesrequires greater charge injection from the soft programming pulse thaneach of the conforming bit lines to overcome an over-erased condition.For some of these embodiments, at least one cell disposed on eachdefective bit line remains below a targeted threshold voltage levelafter a first number of programming cycles. The first number ofprogramming cycles can be greater than two.

The redundant bit lines logically replace defective selected bit linesin the first memory array 110 during the BLISP method adapted tologically replace defective bit lines 801, so that application of thesoft program pulse to the defective bit lines can be prevented.Responsive to an indication of a defective selected bit line the softprogram pulse is applied to a subject redundant bit line that logicallyreplaces the selected defective bit line.

In some of these embodiments, the redundant bit lines also logicallyreplace defective bit lines in the first memory cell array during theapplication of preprogramming, erase and programming cycle pulses, sothat applications of these pulses to the defective bit lines can also beprevented. In some embodiments, both the redundant bit lines and thedefective bit lines are subject to the preprogramming, erase andprogramming cycle pulses.

In some embodiments BLISP method adapted to logically replace defectivebit lines 801, if the redundancy system 170 indicates that the bit lineis defective, the applying 813 of the soft program pulse includes theredundancy system turning off the defective selected bit line so thatthe soft programming voltage level is not applied to cells disposed onthe defective bit line. The applying 813 of the soft program pulse forthis embodiment also includes the redundancy system turning on thesubject redundant bit line so that the soft programming voltage level isapplied to cells disposed on the subject redundant bit line.

The redundancy system 170 can indicate the bit line type correspondingto the selected bit line. In some embodiments, the bit lines in thefirst memory array 110 have addresses. The bit line addresses (shown inFIGS. 2A through 2C, and FIGS. 9A and 9B as A_(o)-A_(P)) can be providedfrom the command logic 150 and counted by the address counter 140.

In some embodiments where the bit lines have addresses, the redundancysystem 170 processing resources can include a redundancy bit linedecoding system 915. The redundancy bit line decoding system 915, shownin FIG. 9B can include a first set of cells 925 and a logic array. Eachcell in the first set of cells 925 stores a bit line type indicationcorresponding to a predetermined bit line address in the first memoryarray 110.

The selecting 811 of a selected bit line can include the decoding system910 receiving bit line selection inputs, such as bit line addresses,corresponding to the selected bit lines. The logic array can compareeach bit line address input with the bit line type indication of the bitline corresponding to the address input.

The applying 813 of the soft program pulse can include generating asignal, such as the second input signal 950 for bit line decoding shownin FIG. 9A. The second input signal 950 can switch off the softprogramming pulse for all of the first memory array 110 cells inresponse to a defective bit line type indication for a selected bitline. The second input signal 950 can comprise a disable line inputsignal 950A for bit line decoding, shown in FIG. 9B as the YDIS signal.The disable line input signal 950A for bit line decoding is adapted todisable the set bit lines in the first memory array 110, for defectiveset bit lines. An enable signal, such as the E_(n0) signal 970-0 in FIG.9C, to switch on the soft programming pulse for the subject redundantbit line can also be generated in response to a defective bit line typeindication.

For example, as depicted in FIGS. 9A-9C, as the first memory cell arraybit line address changes from A_(o)-A_(P), the redundancy systemprocessing resources compare the address information input with thepre-defined defective bit line addresses stored in the first set ofcells 925. If the address is the same as one set of address informationstored in the first set of cells 925, one of the redundancy enablesignals E_(n0)−E_(nx), e.g., E_(n0) 940 for the zero redundancy bitline, or E_(nx), 945 for the x-th redundancy bit line, turns on. Theturned on redundancy enable signal switches off the Y_(n0)−Y_(nm) bitline decode signals by providing a signal to the YDIS disable line 950A,thereby preventing application of the soft programming pulse to thedefective bit line in the first memory cell array. The turned onredundancy enable signal also switches on the corresponding redundantbit line path in the second memory cell array.

For example, if the first indication of a defective bit line correspondsto the third bit line (not shown in FIGS. 2A-2C) in the first memoryarray 110, then the zero redundancy bit line would be turned on, whenthe third bit line was selected. The memory cells disposed in the zeroredundancy bit line would receive the soft repair pulse. All of theY_(n0)-Y_(nm) decode signals would be turned off to prevent the Y_(n2)decode signal from enabling the memory cells on the defective third bitline from receiving the soft repair pulse. If the second indication of adefective bit line corresponds to the seventh bit line (not shown inFIGS. 2A-2C) in the first memory array 110, then the first redundancybit line would be turned on when the seventh bit line was selected. Thememory cells disposed in the first redundancy bit line would receive thesoft repair pulse. All of the Y_(n0)-Y_(nm) decode signals would beturned off to prevent the Y_(n6) decode signal from enabling the memorycells on the defective seventh bit line from receiving the soft repairpulse.

As shown in FIG. 9B the redundancy bit line decoding system disposed inthe redundancy system 910A can include exclusive NOR gates 935 coupledto the bit line address inputs and the corresponding selected bit linetype indications stored in the first set of cells 925. The applying 813of the soft program pulse can include the exclusive NOR gates 935toggling on a coupled redundant bit line enable signal in response to adefective selected bit line indication.

The applying 813 of the soft program pulse can also include respondingto the indicating of the conforming bit line type by generating asignal, such as the Y_(n0) signal 960-0 shown in FIG. 9C, to switch onthe soft programming pulse to the selected bit line.

As discussed above, the BLISP method adapted to logically replacedefective bit lines 801 logically replaces each defective bit line witha redundant bit line when applying 813 the soft programming voltagelevel. In the absence of such replacement, the presence of very lowthreshold voltage cells, or other types of defects, on the defective bitline can result in greater current demand during application of a softrepair pulse to the defective bit line. The increased current demand canbe enough to cause the voltage level to spike. Therefore, applying 813the soft programming voltage level only to the substitute redundant bitline avoids the high current consumption and voltage spiking that wouldoccur if the soft program pulse were applied to the defective bit line.Therefore, the soft program is performed more efficiently.

Another problem that arises for soft programming of defective bit linesis that the voltage on the data line conductor 245 cannot be sustainedat a sufficiently high level for efficient soft programming. Thisproblem, caused by loss of current through the defective (very lowthreshold voltage) bit line cells, is exacerbated when the data lineconductor 245 voltage is provided from a pumping circuit because thepumping circuit is characterized by a limited current supply capability.

The BLISP method can also be implemented in a block erase process asshown in FIG. 8C. The first memory array 110 can include a plurality ofblocks in a block-segmented architecture. The block segmentedarchitecture can be as shown in any of FIGS. 2A-2C, or any other blocksegmented memory array architecture. Each block has at least one bitline. Prior to the soft programming, cells disposed in conforming bitlines disposed in blocks having set erase flags are erased. Cellsdisposed in redundant bit lines corresponding to defective bit linesdisposed in blocks having set erase flags can also be erased prior tothe soft programming. The same erase process can be provided for theBLISP method adapted to logically replace defective bit lines 801.

In some embodiments of the BLISP methods, a pre-program cycle is appliedto the subject bit lines along with the erase and soft program cycles.Such embodiments are illustrated for a generalized soft program in FIG.3B, for a SCIHE soft program in FIG. 3A, and in greater detail for theblock erase and bit line soft program method 802, shown in FIG. 8C. Theblock erase and BLISP process 802 includes the steps discussed above forthe BLISP process 800. The providing 822 the redundancy system step isonly shown in FIG. 8B because this step is performed before any actualprocessing occurs, i.e., before the start step 825. The block erasesteps 825 through 872 are as provided in FIG. 4 of U.S. Pat. No.5,745,410, issued on Apr. 28, 1998, and incorporated by referenceherein. A table providing reference numbers in FIG. 4 of U.S. Pat. No.5,745,410 that correspond to the reference numbers 825 trough 872 inFIG. 8 herein is provided below.

Reference Reference #'s from #'s from FIG. 8 FIG. 4 of Description ofItem herein 5,745,410 Set flags indicating block erase 825  99 Set flagsindicating block soft program (repair) 827  99A Pre-program blocks withset erase flags 829 100 Erase blocks with set erase flags 831 101Deterrnine whether erase time out duration has 833 102 been reachedErase recovery 835 103 Deterinine whether erase recovery time out 836104 duration has been reached Set up erase verify voltages 838 105Determine whether erase verify time out duration 840 N/A has beenreached Evaluate erase flags and test data in selected 842 106 blocksErase flag set deterrnination 844 107 Pass erase verify and not lastleast significant bit 846 108 Increase least significant bit address 848109 Last block determination 852 110 All erase flags reset determination856 111 Erase completion indication 860 112 Pass erase verify and lastleast significant bit 864 113 Reset block erase flag 868 114 Increasemost significant bit and reset least 872 115 significant bit

The BLISP method 800 can be used in conjunction with the erase withSCIHE soft program 300 method, shown in FIG. 3A. This is accomplished byreplacing the SCIHE soft program 350, and soft program recovery 355steps with the BLISP method steps from setting 805 the bit line addressthrough resetting 820 the soft program flags. Similarly, the BLISPmethod 800 can be implemented as part of the erase with generalized softprogram 301 method. This is accomplished by replacing the generalizedsoft program 352, and soft program recovery 355 steps with the BLISPmethod steps from setting 805 the bit line address through resetting 820the soft program flags. As described above, the other BLISP steps, asshown in FIG. 8A, include maintaining 807 the word line voltage,generating 809 the soft program pulse, selecting 811 the selected bitline, and applying 813 the soft program pulse to the subject bit line.The BLISP method can also include soft program recovery 815, anddetermining 817 whether the selected bit line address is the last bitline. The resetting 820 of the soft program flags is described below.

The sector erase and soft program method 802, shown in FIG. 8C includesan algorithm for the embedded erase and soft programming. The commandlogic 150 interprets inputs to set a mode of operation for the read andprogram control circuit 165. The control circuit 165 then generallyexecutes the algorithm, or mode of operation. For embodiments where thefirst memory array 110 includes a plurality of blocks, the method caninclude erasing some of the memory cells. For example, cells disposed inselected conforming bit lines in blocks having erase flags can beerased. Also, cells disposed in subject redundant bit lines logicallyreplacing defective bit lines can be erased, where the replaceddefective bit lines are disposed in blocks having set erase flags.

The block-segmented architecture can be implemented so that certainblocks are not subject to any combination of one or more of thepre-program, erase, and soft program processes. For example if a blockhas a reset flag for a particular process, the pulses associated withthat process are not applied to cells in the block. Instead, the blockswith reset blocks are passed without application of the pulse.

In some embodiments where the selected bit lines have soft programmingflags, the BLISP method 800, and the BLISP method adapted to logicallyreplace defective bit lines 801, can include setting the softprogramming flags for the selected bit lines. Where the bit lines haveaddresses, the BLISP methods can include determining 817 whether theselected bit line address corresponds to a last address.

For example, before the applying 813 of the soft program pulse, theaddress counter 140 can set the selected bit line address to 000. The000-bit line corresponds to the bit line connected to the Y₀₀ signal forthe first block that has a set soft programming flag. After applying 813the soft program pulse for each subject bit line, the BLISP method 800can include the block erase, erase verify, and soft program repair statemachine 125 determining 817 whether the selected bit line addresscorresponds to a last address. This determination is typically madeusing the address counter in the soft program repair state machine 125.The same type of determination can be made for the BLISP method adaptedto logically replace defective bit lines 801.

If the selected bit line address corresponds to the last address, theBLISP methods can include resetting 820 the soft programming flagscorresponding to the selected bit lines. The resetting 820 of the softprogramming flags is typically performed by the block erase, eraseverify, and soft program repair state machine 125. If the selected bitline address does not correspond to the last address, the BLISP methodsinclude incrementing 819 the bit line address. The maintaining 807 wordline voltage, selecting 811 selected bit line, and applying 813 the softprogram pulse steps are then performed for a next subject bit linecorresponding to the incremented address.

A second aspect of the invention provides a method for correcting anover-erase condition within a non-volatile memory array. The methodincludes providing a first non-volatile memory array, such as the firstmemory array 110 in FIGS. 1A and 1B, in an integrated circuit. The arrayhas a plurality of floating gate memory cells 400. Each floating gatememory cell 400, as shown in FIG. 4 and described above in the SCIHEsection, includes a stacked pair of gates including a control gate 401and a floating gate 402. The gates are spaced above a channel region, orwell 404, and are interposed between a source 403 and a drain 405region. The memory cells are arranged in bit lines. The method includesselecting 811 a selected bit line. The method for correcting anover-erase condition also includes applying a first voltage to thecontrol gate 401, an active current limiter (or sink 420) to the source403 region, a non-positive voltage to the channel region, and a positivesecond voltage to the drain 405 region of memory cells disposed on asubject bit line corresponding to the selected bit line. The applicationof the first voltage corresponds to maintaining 807 the word linevoltage, and the application of the second voltage corresponds to theapplying 813 of the soft program pulse.

In some embodiments of method for correcting an over-erase condition,the subject bit line comprises the selected bit line. In someembodiments, the first voltage is between minus one volt and six volts.

In some embodiments of method for correcting an over-erase condition,the first non-volatile memory array includes conforming bit lines anddefective bit lines. The selecting includes indicating a bit line typecorresponding to the selected bit line. The integrated circuit includesa redundancy system 170 including a second non-volatile memory arrayhaving a plurality of memory cells, such as the second memory array 905shown in FIG. 9C, and processing resources. Each memory cell in thesecond array has the same features described above for the first arraymemory cells. The second memory array memory cells are arranged asredundant bit lines. The processing resources are adapted to perform theindicating. The bit line types include a conforming bit line type and adefective bit line type. In response to indicating the conforming bitline type, the subject bit line comprises the selected bit line. Inresponse to indicating the defective bit line type, the second voltageis not applied to the selected bit line, and the subject bit lineincludes a subject redundant bit line logically replacing the selectedbit line

Integrated Circuit for Bit Line Soft Programming

A third aspect of the invention provides an integrated circuit capableof implementing the bit line soft programming (BLISP) method. Theintegrated circuit comprises a first memory array 110, processingresources, word lines (such as word lines WL₀ through WL_(N) in FIGS. 2Athrough 2C), and a control circuit 165. The first memory array 110 hasfloating gate memory cells 400 disposed on bit lines, such as the firstlocal bit line 203 and the second local bit line 206. For purposes ofbit line selection, the processing resources typically address suchlocal bit lines, but for the architecture illustrated in FIGS. 2Athrough 2C, the addressable bit lines include the first global bit line224 and the second global bit line 227. Each of the floating gate memorycells 400 in the first memory array has a control gate 401, a floatinggate 402, a source 403, and a drain 405. The processing resources areadapted to select 811 selected bit lines for soft programming. The wordlines are in communication with the control gates 401. The controlcircuit 165 is coupled with the processing resources to apply 813 a softprogram pulse to the floating gate memory cells 400 disposed on subjectbit lines, the subject bit lines corresponding to selected bit lines.

In some embodiments of the integrated circuit, the subject bit linescomprise the selected bit lines. In some embodiments, the selected bitlines have corresponding soft programming flags; and the control circuit165 is adapted to set the soft program flags for the selected bit linesprior to the maintaining.

In some embodiments of the integrated circuit, the first memory array110 is arranged in blocks of memory cells. Each of the blocks has atleast one bit line, and a block erase flag corresponding to the block. Ablock erase/erase verify/soft program circuit 125, otherwise referred toherein as a “state machine circuit”, and the processing resources arecoupled to erase, prior to the soft programming, cells disposed in thesubject bit lines disposed in blocks having set erase flags.

For some of the embodiments where the first memory array 110 is arrangedin blocks of memory cells, the bit lines have addresses. The blockerase/erase verify/soft program circuit 125 is adapted to determinewhether the selected bit line address corresponds to a last addressafter the applying. In response to the selected bit line addresscorresponding to the last address, the block erase/erase verify/softprogram circuit 125 resets the soft programming flags. In response tothe selected bit line address not corresponding to the last address, theaddress counter 140 increments the bit line address, and to cause theintegrated circuit to repeat the soft program for a next bit linecorresponding to the incremented address.

In some embodiments of the integrated circuit, the control circuit 165is adapted to maintain the word lines at a predetermined voltage level.The voltage level set on the word lines is between approximately aboveground and 0.5 volts. The applying includes applying 813 a soft programpulse to the subject bit lines while maintaining 807 the word linevoltage. In some embodiments, the soft programming pulse repairsover-erased cells so that the over-erased cells may be reprogrammedabsent a previously applied repair verify operation.

In some embodiments of the integrated circuit, the first memory array110 includes a plurality of blocks, arranged in rows and columns. Eachblock includes the bit lines, the word lines, and source lines. Thecontrol circuit 165 is coupled to the bit lines, the source lines, andthe word lines. The control circuit 165 is adapted to set thresholdvoltages of the cells in selected blocks to a low threshold voltage. Thecontrol circuit 165 includes voltage supply circuits to supply a voltagesequence to lower the threshold voltages of cells in each selectedblock. The voltage sequence results in a first group of cells havingthreshold voltages lowered below a selected limit for the thresholdvoltage. The voltage supply circuits supply a soft programming pulse tosubject bit lines disposed in each selected block during a softprogramming time interval across the source lines and the bit lines,while setting the voltage on the word lines to a level below theselected limit. The current consumption for the circuit during softprogramming is fixed. The higher threshold voltage bits, i.e., nonover-erased cells therefore consume less current than the over-erasedcells; and the logic states of the higher threshold cells are notaffected by the soft program.

In some embodiments of the third aspect, the first memory array isarranged in rows and columns. The integrated circuit includes well linescoupled to wells of respective rows of cells in the first memory array110. The control circuit 165 includes voltage supply circuits to supplya well voltage on the well lines corresponding to the selected bitlines. The control circuit 165 couples a current limiter circuit 500 tothe source lines corresponding to the selected bit lines. In someembodiments, the processing resources include a soft program repairstate machine and an address counter 140.

In some embodiments of the integrated circuit, the first memory array110 bit lines comprise defective bit lines and conforming bit lines. Theintegrated circuit includes a redundancy system 170 having a secondarray of floating gate memory cells 400 disposed on redundant bit lines,and processing resources. Each of the floating gate memory cells 400 inthe second memory array 905 has a control gate 401, a floating gate 402,a source 403, and a drain 405. The redundant bit lines logically replacethe defective bit lines. The processing resources adapted to indicatebit line types of the selected bit lines in the first memory array aredisposed in the redundancy system 170. The subject bit lines includeselected conforming bit lines and subject redundant bit lines logicallyreplacing selected defective bit lines. The control circuit 165 isadapted to cooperate with the redundancy system 170 to prevent applyingof the soft program to floating gate memory cells 400 disposed ondefective bit lines.

For some of the embodiments of the integrated circuit having aredundancy system 170, the applying includes applying 813 a soft programpulse. The bit lines in the first memory array 110 have addresses. Theredundancy system 170 processing resources include a redundancy bit lineaddress decoding system, referred to herein as a redundancy bit linedecoding system 915. The redundancy bit line decoding system 915includes a first set 925 of cells, a logic array, and processingresources. Each cell in the first set 925 of cells stores a bit linetype indication corresponding to a predetermined bit line address. Thelogic array is adapted to compare each bit line address input with thebit line type indication corresponding to the address input. Theprocessing resources are adapted to receive bit line address inputscorresponding to the selected bit lines. The processing resourcesrespond to a defective bit line type indication by generating a signalto switch off the soft programming pulse for the first memory array bitlines. The processing resources respond to a conforming bit line typeindication by generating a signal to switch on the soft programmingpulse for the selected bit line.

For some of the embodiments of the integrated circuit having aredundancy system 170, the applying includes applying 813 a soft programpulse. Responsive to an indication of the conforming bit line type, theredundancy system 170 processing resources are adapted to enableapplying 813 of the soft program pulse to the selected bit lines.Responsive to an indication of the defective bit line type, theprocessing resources are adapted to disable applying 813 of the softprogram pulse to the selected bit lines, and enable application of thesoft program pulse to the subject redundant bit lines logicallyreplacing the selected bit lines.

For some of the embodiments of the integrated circuit having aredundancy system 170, the first memory array 110 is arranged in blocksof memory cells. Each of the blocks has at least one bit line, and ablock erase flag corresponding to the block. The control circuit 165 andthe redundancy system 170 processing resources are coupled to erase,prior to the soft programming, cells disposed in the selected conformingbit lines disposed in blocks having set erase flags. The control circuit165 and the redundancy system 170 processing resources are also coupledto erase, prior to the soft programming, cells disposed in the subjectredundant bit lines logically replacing defective bit lines, thedefective bit lines disposed in blocks having set erase flags.

For some of the embodiments of the integrated circuit having aredundancy system 170, the cells in the first memory array 110 and thesecond memory array 905 are arranged in rows and columns. The integratedcircuit includes well lines coupled to wells 404 of respective rows ofcells in the first memory array 110 and coupled to respective rows ofcells in the second memory array 905. The control circuit 165 includesvoltage supply circuits supply a well voltage on the well linescorresponding to the selected bit lines. The control circuit 165 couplesan active current limiter circuit 500 to the source lines correspondingto the selected bit lines.

For some of the embodiments of the integrated circuit having aredundancy system 170, the applying includes applying 813 a soft programpulse. The bit lines in the first memory 110 array have addresses. Theredundancy system 170 processing resources include a redundancy bit linedecoding system 915 having a first set 925 of cells. Each cell in thefirst set 925 stores a bit line type indication corresponding to apredetermined bit line address. The redundancy bit line decoding system915 also has a logic array. The logic array is adapted to compare eachbit line address input with the bit line type indication correspondingto the address input. The decoding system 910 is adapted to receive bitline address inputs corresponding to the selected bit lines.

The redundancy bit line decoding system 915 processing resources areadapted to respond to a defective bit line type indication by generatinga signal to switch off the soft programming pulse for the first memoryarray 110 bit lines, and to switch on the soft programming pulse for thesubject redundant bit line. The redundancy bit line decoding system 915processing resources are adapted to respond to a conforming bit linetype indication by generating a signal to switch on the soft programmingpulse to the selected bit line. The decoding system 910 can includeexclusive NOR gates 935 coupled to the bit line address inputs and thecorresponding bit line type indications. Responsive to defectiveselected bit line type indications, the exclusive NOR gates 935 areadapted to toggle on the coupled redundant bit line enable signals.

A fourth aspect of the invention provides a floating gate memorycomprising floating gate memory cells 400, a first circuit, and a secondcircuit. The first circuit can include a bit line decoder system 910, asshown in FIG. 9A. The second circuit can include a gate switch 410, asource switch 411, a well switch 412, and a drain switch 413, as shownin FIG. 4. Each of the floating gate memory cells 400 has a control gate401, a floating gate 402, a source 403, and a drain 405. The floatinggate memory cells 400 are disposed on bit lines in a first memory array.The first circuit is adapted to select selected bit lines. The secondcircuit is adapted to soft program floating gate cells in subject bitlines. The subject bit lines correspond to the selected bit lines. Thesecond circuit is also adapted to supply a gate voltage to the controlgate 401, a current limiter circuit 500 to the drain 405, a well voltageto a well 404, and a source voltage to the source 403 of the floatinggate memory cells 400 disposed on the subject bit lines. Note that thecurrent limiter circuit 500 shown in FIG. 5 comprises an active currentlimiter.

For some of the embodiments, the memory includes floating gate memorycells having a drain 405, a control gate 401, a floating gate 402, awell 404, and a source 403. The floating gate cells are disposed on bitlines in a second memory array 905. The second circuit is adapted tosupply a gate voltage to the control gate 401, an active current limiterto the drain 405, a well voltage to the well 404, and a source voltageto the source 403 of the cells in the second memory array 905. Thesubject floating gate cells are also disposed on redundant bit lines.The redundant bit lines are disposed in the second memory array 905. Theredundant bit lines logically replace the defective bit lines in thefirst memory array 110.

The details of some of the different embodiments of the integratedcircuit correspond to the details provided above in the BLISP method 800section.

The foregoing description of embodiments of the invention has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. Obviously, many modifications and variations will be apparentto practitioners skilled in this art. It is intended that the scope ofthe invention be defined by the following claims and their equivalents.

What is claimed is:
 1. In a floating gate integrated circuit having afirst memory array including a plurality of bit lines identified by bitline addresses, the bit lines coupled to floating gate memory cellsconfigured to be programmed and erased, wherein each of the cells has adrain, a source, and a control gate, and wherein the control gates ofthe cells are in communication with word lines, a method for softprograming floating gate memory cells comprising: maintaining the wordlines at a predetermined word line voltage level; generating a softprogramming pulse having a soft programing voltage level; selecting aselected bit line in response to a bit line address; and applying thesoft programming voltage level to cells disposed on a subject bit linecorresponding to the selected bit line.
 2. The soft programming methodof claim 1, wherein the subject bit line comprises the selected bitline.
 3. In a floating gate integrated circuit having a first memoryarray including a plurality of bit lines, the bit lines corresponding tofloating gate memory cells configured to be programmed and erased,wherein each of the cells has a drain, a source, and a control gate, andwherein the control gates of the cells are in communication with wordlines, a method for soft programming floating gate memory cellscomprising: maintaining the word lines at a predetermined word linevoltage level; generating a soft programming pulse having a softprogramming voltage level; selecting a selected bit line; and applyingthe soft programming voltage level to cells disposed on a subject bitline corresponding to the selected bit line, wherein: the first memoryarray includes conforming bit lines and defective bit lines; theselecting includes indicating a bit line type corresponding to theselected bit line, the integrated circuit includes a redundancy systemincluding a second memory array and processing resources, the secondmemory array having redundant bit lines, the processing resourcesadapted to perform the indicating, the bit line types including aconforming bit line type and a defective bit line type; responsive toindicating the conforming bit line type, the subject bit line comprisingthe selected bit line; and responsive to indicating the defective bitline type, the subject bit line comprising a subject redundant bit line,the subject redundant bit line logically replacing the selected bitline.
 4. The soft programming method of claim 1, wherein: the selectedbit lines have corresponding soft programming flags, and the methodincludes, prior to the maintaining, setting the soft program flags forthe selected bit lines.
 5. The soft programming method of claim 1,wherein the first memory array includes a plurality of blocks, eachblock having at least one bit line, and wherein prior to the softprogramming the method includes erasing cells disposed in the bit linesdisposed in blocks having set erase flags.
 6. The soft programmingmethod of claim 1, wherein the predetermined word line voltage level isbetween approximately above ground and 0.5 volts.
 7. The softprogramming method of claim 1, wherein the soft programming pulserepairs over-erased cells so that the over-erased cells may bereprogrammed absent a previously applied repair verify operation.
 8. Thesoft programming method of claim 1, wherein: the integrated circuitincludes processing resources including a redundancy bit line decodingsystem; the selecting includes the decoding system receiving a bit lineaddress input corresponding to the selected bit line; and the applyingincludes the processing resources providing a signal to switch on thesoft program pulse to the subject bit line.
 9. The soft programmingmethod of claim 3, wherein at least one of the defective bit linesrequires greater charge injection from the soft programming pulse thaneach of the conforming bit lines to overcome an over-erased condition.10. The soft programming method of claim 3, wherein the first memoryarray includes a plurality of blocks, each of the blocks having at leastone bit line, and wherein prior to the soft programming the methodincludes: erasing cells disposed in conforming bit lines disposed inblocks having set erase flags; and erasing cells disposed in subjectredundant bit lines logically replacing defective bit lines disposed inthe blocks having set erase flags.
 11. The soft programming method ofclaim 3, wherein responsive to the indicating of the defective bit linetype, the applying includes: the redundancy system turning off theselected bit line so that the soft programming voltage level is notapplied to cells disposed on the selected bit line; and the redundancysystem turning on the subject redundant bit line so that the softprogramming voltage level is applied to cells disposed on the subjectredundant bit line.
 12. The soft programming method of claim 3, wherein:the bit lines in the first memory array have addresses, the processingresources include a redundancy bit line decoding system having a firstset of cells and a logic array, each cell in the first set storing a bitline type indication corresponding to a predetermined bit line address;the indicating includes: the redundancy bit line decoding systemreceiving a bit line address input corresponding to the selected bitline; the logic array comparing the bit line address input with the bitline type indication of the bit line corresponding to the address input;and the applying includes: responsive to the indicating of the defectivebit line type, generating a signal to switch off the soft programmingpulse for all of the first memory array cells, and to switch on the softprogramming pulse for the subject redundant bit line; and responsive tothe indicating of the conforming bit line type, generating a signal toswitch on the soft programming pulse to the selected bit line.
 13. Thesoft programming method of claim 4, wherein after the applying, themethod includes: determining whether the selected bit line addresscorresponds to a last address; responsive to the selected bit lineaddress corresponding to the last address, resetting the softprogramming flags for the selected bit lines; and responsive to theselected bit line address not corresponding to the last address,incrementing the bit line address and repeating the maintaining,generating, selecting, and applying for a next bit line corresponding tothe incremented address.
 14. The soft programming method of claim 8,wherein at least one cell disposed on each defective bit line remainsbelow a targeted threshold voltage level after a first number ofprogramming cycles.
 15. The soft programming method of claim 12,wherein: the redundancy bit line decoding system includes an exclusiveNOR gate coupled to the bit line address input and the corresponding bitline type indication; and the applying includes, responsive to theindicating of the defective bit line type, the corresponding exclusiveNOR gate toggling on a coupled redundant bit line enable signal.
 16. Thesoft programming method of claim 14, wherein the first number ofprogramming cycles is greater than two.